Semiconductor-on-insulator (SOI) strained active area transistor
US7585711B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2006 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Sep 1, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D87/00
Abstract
A selectively strained MOS device such as selectively strained PMOS device making up an NMOS and PMOS device pair without affecting a strain in the NMOS device the method including providing a semiconductor substrate comprising a lower semiconductor region, an insulator region overlying the lower semiconductor region and an upper semiconductor region overlying the insulator region; patterning the upper semiconductor region and insulator region to form a MOS active region; forming an MOS device comprising a gate structure and a channel region on the MOS active region; and, carrying out an oxidation process to oxidize a portion of the upper semiconductor region to produce a strain in the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.