Method of fabricating multi-gate transistor and multi-gate transistor fabricated thereby
US7585734B2 · kind B2 · utility
39Cited by
18References
14Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 5, 2008 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Mar 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/673
Abstract
Provided are a method of fabricating an improved multi-gate transistor and a multi-gate transistor fabricated using the method, in which an active pattern is formed on a substrate, the active pattern having two or more surfaces on which channel regions are to be formed, a gate insulating layer is formed on the channel regions, and a patterned gate electrode is formed on the gate insulating layer while maintaining a shape conformal to the active pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.