Process for manufacturing a multilayer structure made from semiconducting materials
US7585748B2 · kind B2 · utility
16Cited by
13References
20Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Mar 24, 2006 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Jul 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1903
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The invention relates to a process for manufacturing a multilayer structure made from semiconducting materials that include an active layer, a support layer and an electrically insulating layer between the active layer and the support layer. The process includes the step of modifying the density of carrier traps or the electrical charge within the electrically insulating layer in order to minimize electrical losses in the structure support layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.