Semiconductor memory device and method of manufacturing the same
US7585787B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2007 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Feb 7, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
Abstract
A semiconductor memory device, e.g., a charge trapping type non-volatile memory device, may include a charge trapping structure formed in a first area of a substrate and a gate structure formed in a second area of the substrate. The charge trapping structure may include a tunnel oxide layer pattern, a charge trapping layer pattern and a dielectric layer pattern of aluminum-containing tertiary metal oxide. The gate structure may include a gate oxide layer pattern, a polysilicon layer pattern and an ohmic layer pattern of aluminum-containing tertiary metal silicide. A first electrode and a second electrode may be formed on the charge trapping structure. A lower electrode and an upper electrode may be provided on the gate structure. The dielectric layer pattern may have a higher dielectric constant, and the ohmic layer pattern may have improved thermal stability, thereby enhancing programming and erasing operations of the charge trapping type non-volatile memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.