Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US7586116B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2006 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Apr 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
Abstract
A semiconductor device may include a substrate, an insulating layer adjacent the substrate, and a semiconductor layer adjacent a face of the insulating layer opposite the substrate. The device may further include source and drain regions on the semiconductor layer, a superlattice adjacent the semiconductor layer and extending between the source and drain regions to define a channel, and a gate overlying the superlattice. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.