Circuit device including vertical transistors connected to buried bitlines and method of manufacturing the same
US7586149B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2006 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | May 19, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A circuit device including vertical transistors connected to buried bitlines and a method of manufacturing the circuit device. The circuit device includes a semiconductor substrate including a peripheral circuit region and left and right cell regions at both sides of the peripheral circuit region, bottom active regions arranged on the semiconductor substrate to be spaced apart from one another in a column direction and to extend from the peripheral circuit region alternately to the left cell region and the right cell region in a row direction, channel pillars protruding from the bottom active regions in a vertical direction and arranged to be aligned in the row direction and spaced apart from one another, gate electrodes provided with a gate dielectric layer and attached to surround side surfaces of the channel pillars, and buried bitlines extending along the bottom active regions, the bottom active regions including a bottom source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.