Semiconductor wafer having embedded electroplating current paths to provide uniform plating over wafer surface
US7586175B2 · kind B2 · utility
15Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2006 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Nov 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer having multi-layer metallization structures that are fabricated to include embedded interconnection structures which serve as low-resistance electroplating current paths to conduct bulk electroplating current fed to portions of a metallic seed layer at peripheral surface regions of the wafer to portions of the metallic seed layer at inner/central surface regions of the semiconductor wafer to achieve uniformity in metal plating in chip regions across the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.