Reducing bit line leakage current in non-volatile memories
US7586787B2 · kind B2 · utility
12Cited by
11References
20Claims
0Family size
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Key dates
| Filing date | Sep 20, 2007 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Nov 26, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program word line is connected to a memory cell and the memory cell includes a plurality of transistors. In another example embodiment, an unselected memory cell is biased to a negative bias voltage during read operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.