Semiconductor CP (circuit probe) test management system and method
US7587293B2 · kind B2 · utility
1Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 9, 2007 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Oct 3, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2894
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for semiconductor CP (circuit probe) test management. A control request message is received from a client computer, directing alignment of a probe unit or a wafer in a prober, attachment of a probe pin of the probe unit on a specific area of the wafer, and subsequent execution of CP testing. At least one control command corresponding to the control request message is issued to direct the prober for alignment of the probe unit or the wafer, attachment of the probe pin of the probe unit on the specific area of the wafer, and subsequent execution of CP testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.