Serializer-deserializer circuits formed from input-output circuit registers
US7587537B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 2007 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Nov 30, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/145
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Input-output circuitry for integrated circuits such as programmable logic device integrated circuits is provided. The input-output circuitry can be configured to operate in a single-ended data mode or a serializer-deserializer mode using programmable routing circuitry such as programmable multiplexers. In single-ended data mode, data registers in the single-ended input-output circuitry may be used to handle transmitted and received single-ended data. In serializer-deserializer mode, the data registers may be configured to form a shift register. The shift register may be used in a serializer-deserializer circuit. Parallel-to-serial and serial-to-parallel data conversion operations may be performed using the shift register. The serializer-deserializer circuit may be connected to differential input-output circuitry such as a differential transmitter circuit or a differential receiver circuit. The data registers may be configured to operate as positive-edge-triggered or negative-edge-triggered devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.