Patent · US Active

Test pattern generation in residue networks

US7587646B1 · kind B1 · utility

1Cited by

5References

28Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Thomas J. Snethen · Beacon, US
Carolyn Asher · Endicott, US

Key dates

Filing date	Jun 20, 2008
Grant date	Sep 8, 2009
Priority date	—
Expiry date	Jun 20, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/318547
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Generating a near-minimal test pattern set for overlapping residue circuit trees in a residue network includes resolving a residue function of residue circuits through the network and making note of any gate at which the residue function thereof does not produce the assigned vector output for a given assigned set of input vectors. Where such gates cannot be resolved during one set of vector assignments, the test set that is complete up to the offending gate may be saved, and resolution of the residue function may be started from another node in the network. Multiple test sets may be generated, the combined application of which will exhaustively test each gate in the network.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.