Controlling system for gate formation of semiconductor devices
US7588946B2 · kind B2 · utility
25Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2005 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Aug 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.