Method for fabricating a top conductive layer in a semiconductor die and related structure
US7589009B1 · kind B1 · utility
14Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2006 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Jun 1, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to an exemplary embodiment, a method for fabricating a top conductive layer in a semiconductor die includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the semiconductor die. The method further includes extending the through-wafer via opening through a substrate of the semiconductor die to reach a target depth. The method further includes forming a through-wafer via conductive layer in the through-wafer via opening, and concurrently forming the top conductive layer over an exposed top metal segment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.