Method for fabricating semiconductor memory device
US7589012B1 · kind B1 · utility
14Cited by
2References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 30, 2008 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Jun 30, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a method for fabricating a semiconductor memory device that can prevent oxidation of bit lines when forming an interlayer dielectric for isolating the bit lines. The bit line is formed on a semiconductor substrate where an underlying structure is formed. A silicon on dielectric (SOD) layer is formed on the resulting structure where the bit line is formed. A heat treatment can be performed on the SOD layer with a partial pressure ratio of water vapor (H2O) to hydrogen (H2) in a range of about 1×10−11 to about 1.55 at a temperature in a range of about 600° C. to about 1,100° C.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.