Layout structure in semiconductor memory device comprising global work lines, local work lines, global bit lines and local bit lines
US7589367B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2005 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Feb 23, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line, and a global bit line and a local bit line, and individually disposing all of the global word line, the local word line, the global bit line and the local bit line at conductive layers among at least three layers; at least two of the global word line, the local word line, the global bit line and the local bit line are together disposed in parallel on one conductive layer. Signal lines constituting a semiconductor memory device are disposed in a hierarchical structure, whereby a semiconductor memory device advantageously having high integration, high speed and high performance may be obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.