Method for forming integrated circuit utilizing dual semiconductors

US7589380B2 · kind B2 · utility

Assignee

• Noble Peak Vision Corp. · US

Inventors

• Conor S. Rafferty · Newton, US
• Clifford A. King · Kingston, US

Key dates

• Filing date: Sep 7, 2005
• Grant date: Sep 15, 2009
• Expiry date: Jan 1, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/01

Abstract

A monolithically integrated electronic circuit using two different semiconductor layers which are separated by a dielectric layer. Transistors formed in the upper semiconductor layer are connected to transistors formed in the lower semiconductor layer via conventional wiring. Preferably, one layer of transistors is of one polarity, N-type or P-type, while the second layer of transistors is of the opposite polarity.