Reversible input/output delay line for bidirectional input/output blocks
US7589557B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2006 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Jun 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01759
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input/output (I/O) structure includes a delay element usable for the input path, the output path, or both input and output paths in a user design. In a first mode, the delay element is included in the input path. In a second mode, the delay element is included in the output path. In a third mode, the I/O structure includes the delay in both outgoing signal paths and incoming signal paths, e.g., by utilizing an output tristate signal to control the direction of the delay line. When the output buffer is driving, the delay is inserted in the output path. When the output buffer is tristated, the delay is inserted in the input path. Thus, a single delay element is dynamically shared by both input and output signals that use the same I/O pad. In an optional fourth mode, the delay element is bypassed by both input and output signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.