Semiconductor device having three dimensional structure
US7589992B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2007 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Dec 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.