PVT compensated auto-calibration scheme for DDR3
US7590008B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2007 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Dec 27, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. This includes adjusting read and write DQS signal timing for each DQ/DQS group, as well as inserting or bypassing registers when timing errors are more than one clock cycle. Timing skew caused by trace and driver mismatches between CK, DQ, and DQS signals are compensated for. One or more of these calibrations may be updated by a tracking routine during device operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.