Parameterizable compact network processor for low-level communication with an integrated circuit
US7590137B1 · kind B1 · utility
9Cited by
9References
7Claims
0Family size
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Key dates
| Filing date | Nov 22, 2005 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Jul 26, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/3808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A network processor, disposed on an integrated circuit can include an ingress unit having a dual port block random access memory and an egress unit having a dual port block random access memory. The network processor further can include a network interface configured to write packetized data to the ingress unit and read packetized data from the egress unit as well as a coordination processor configured to coordinate movement of data between the network interface, the ingress unit, and the egress unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.