DFE margin test methods and circuits that decouple sample and feedback timing
US7590175B2 · kind B2 · utility
9Cited by
44References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2006 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Feb 4, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03146
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.