Programmable logic device integrated circuit with communications channels having sharing phase-locked-loop circuitry
US7590211B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 17, 2006 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Feb 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Integrated circuits such as programmable logic device integrated circuits are provided that have resource-efficient receiver circuitry. In source-synchronous system environments, an integrated circuit receives data on multiple buses, each of which has a reference clock signal and associated data signals. One of the reference clocks is provided to a phase-locked-loop circuit, which generates a serial clock and parallel clock for capturing and deserializing data for one of the buses. Each additional bus has an associated phase detector and delay-locked loop in place of a phase-locked loop. The phase detector and delay-locked loop in each additional bus shift the serial clock from the phase-locked loop to produce a serial clock for the additional bus. A parallel clock for each additional bus may be produced using a divider.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.