Monitor implementation in a multicore processor with inclusive LLC
US7590805B2 · kind B2 · utility
4Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2005 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Apr 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/306
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus to implement monitor primitives when a processor employs an inclusive shared last level cache. By the employing an inclusive last level cache, the processor is almost always able to complete a monitor transaction without requiring self snooping through the system interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.