Methods and apparatuses for external delay test of input-output circuits
US7590902B1 · kind B1 · utility
12Cited by
91References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2006 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Dec 25, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318508
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I-Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric Measurement Unit (PMU) capability, and various tests performed on the I-Os by the on-chip testing logic, the test vector patterns supplied by the external testing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.