Method and apparatus for fixing best case hold time violations in an integrated circuit design
US7590957B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2006 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Oct 17, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure is directed to a method and apparatus for fixing hold violations in an integrated circuit design. The method and apparatus trace upstream along a path in the design corresponding to the hold violation, from an end point of the path toward a start point of the path, until an element is reached that corresponds to the start point or has a fanout exceeding a predetermined fanout limit. The method and apparatus then generate an output that defines a location in the design at which to insert a delay element, such that the delay element is connected to an input of an element downstream of the element reached during tracing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.