Embedding device in substrate cavity
US7592202B2 · kind B2 · utility
7Cited by
3References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2006 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Apr 11, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention is a technique to reduce interconnect length between devices. A cavity is formed in a substrate having a substrate surface. The cavity has a depth. A first device having a device surface and a thickness is placed into the cavity. The thickness matches the depth such that the device surface is approximately planar with the substrate surface. The first device is attached to a second device via bumps on the second device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.