Semiconductor transistor with multi-level transistor structure and method of fabricating the same
US7592625B2 · kind B2 · utility
2Cited by
3References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 11, 2006 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Sep 19, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Example embodiments relate to a semiconductor device and a method of fabricating the same. The device may include a semiconductor substrate including a peripheral region and a cell array region, wherein the substrate in the cell array region may be recessed lower than the peripheral region, a plurality of cell transistor layers stacked in the cell array region, and a plurality of peripheral circuit transistors formed in the peripheral region. The cell transistor layers may be formed in the cell array region at a lower level than the peripheral region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.