Stress relaxation for top of transistor gate
US7592653B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 24, 2006 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Jun 22, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/792
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved way to apply tensile or compressive stress to one or more transistors on a semiconductor device is described. A portion of the tensile or compressive stress liner may be removed or modified such that a reduced amount of stress, or even no stress, is applied above the transistor gate. This may cause edges of the stress liner to be adjacent to and on either side of the channel, thus, increasing the stress effect. To produce this stress liner structure, the stress liner may be applied and then a portion of the stress liner is modified to reduce the stress in that portion, such as through ion implantation. The stress liner portion may be modified to have a reduced stress by, for example, implanting certain ions such as germanium or xenon ions therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.