Microelectronic package and method of cooling same
US7592697B2 · kind B2 · utility
48Cited by
1References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2007 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Oct 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16251
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic package comprises a chip stack (110) that includes a substrate (111), a first die (112) over the substrate and a second die (113) over the first die, a first underfill layer (114) between the substrate and the first die, and a second underfill layer (115) between the first die and the second die. The microelectronic package further comprises a fluidic microchannel system (120) in the chip stack, and the fluidic microchannel system comprises a fluid inlet (121) and a fluid outlet (122) connected to each other by a fluidic passage (123).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.