Method for using digital PLL in a voltage regulator
US7592846B2 · kind B2 · utility
3Cited by
8References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2007 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Dec 7, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.