Memory device with reduced reading latency
US7593263B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2007 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Feb 1, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for data storage includes providing a memory, which includes first memory cells having a first reading latency and second memory cells having a second reading latency that is higher than the first reading latency. An item of data intended for storage in the memory is divided into first and second parts. The first part is stored in the first memory cells and the second part is stored in the second memory cells. In response to a request to retrieve the item of data from the memory, the first part is read from the first memory cells and provided as output. The second part is read from the second memory cells, and provided as output subsequently to outputting the first part.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.