Processor reduction unit for accumulation of multiple operands with or without saturation
US7593978B2 · kind B2 · utility
27Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 7, 2004 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Aug 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor having a reduction unit that sums m input operands plus an accumulator value, with the option of saturating after each addition or wrapping around the result of each addition. The reduction unit also allows the m input operands to be subtracted from the accumulator value by simply inverting the bits of the input operands and setting a carry into each of a plurality of reduction adders to one. The reduction unit can be used in conjunction with m parallel multipliers to quickly perform dot products and other vector operations with either saturating or wrap-around arithmetic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.