Patent · US Active

Effective caching mechanism with comparator coupled to programmable registers to store plurality of thresholds in order to determine when to throttle memory requests

US7594042B2 · kind B2 · utility

7Cited by

5References

15Claims

0Family size

Assignee

Intel Corporation · US

Inventor

Su Wei Lim · Klang, MY

Key dates

Filing date	Jun 30, 2006
Grant date	Sep 22, 2009
Priority date	—
Expiry date	Dec 7, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/1425
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system includes a plurality of bus masters that generate direct memory access requests to access a protected memory device. Before granting the access, the system checks for memory protection information stored in a cache. The cache is shared by the bus masters and allocation of the cache entries is prioritized among the bus masters.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.