Parity error checking and compare using shared logic circuitry in a ternary content addressable memory
US7594158B2 · kind B2 · utility
7Cited by
20References
12Claims
0Family size
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Key dates
| Filing date | Aug 26, 2005 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Apr 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for performing, using smaller, more efficient shared logic circuitry, the parity checking function and the compare function in a mutually exclusive manner in different cycles of a ternary content addressable memory are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.