Parallel optimization using independent cell instances
US7594203B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2007 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | May 27, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for parallel optimization of an integrated circuit design based on the use of sets of cell instances that are independent from each other. Multiple changes to a design are analyzed in parallel by ensuring that no two cell instances that are being changed are in the same fan-in and fan-out cones. This property allows full timing analysis to be performed on a design such that multiple alternatives are explored in parallel and accurate results are obtained. By ordering the choice of cell instances to change and by ordering the alternatives to try, a greater degree of optimization is found earlier in the process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.