Method and apparatus for performing layout-driven optimizations on field programmable gate arrays
US7594204B1 · kind B1 · utility
6Cited by
8References
17Claims
0Family size
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Key dates
| Filing date | Oct 6, 2003 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Oct 25, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying a group of components associated with a critical signal in the system. A first copy and a second copy of the group of components are generated where the first copy is driven by a first signal at a first state and the second copy is driven by a second signal at a second state. The system is configured to select an output of one of the first copy and the second copy in response to the critical signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.