Low stress thin film microshells
US7595209B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2007 |
| Grant date | Sep 29, 2009 |
| Priority date | — |
| Expiry date | Aug 25, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Multi-layered, planar microshells having low stress for encapsulation of devices such as MEMS and microelectronics. The microshells may include a perforated pre-sealing layer, below which a sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. The sealing layer may further include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. The various layers may be formed employing processes having opposing stresses to tune the residual stress of the multi-layered microshell. In an embodiment, the hermetic layer is a metal which is deposited with a process tuned to impart a tensile stress to lower the residual stress in the microshell below the magnitude of cumulative stress present in sealing layer and pre-sealing layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.