Semiconductor device including multiple rows of peripheral circuit units
US7595561B2 · kind B2 · utility
2Cited by
6References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2006 |
| Grant date | Sep 29, 2009 |
| Priority date | — |
| Expiry date | Jan 18, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device including an internal circuit, multiple rows of peripheral circuit units are electrically connected to the internal circuit and arranged on at least one peripheral edge of the internal circuit. Also, a plurality of pads are arranged on the peripheral edge of the internal circuit. Each of the pads is electrically connected to one of the peripheral circuit units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.