Method and apparatus for compensating for variances of a buried resistor in an integrated circuit
US7595681B2 · kind B2 · utility
2Cited by
10References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 19, 2006 |
| Grant date | Sep 29, 2009 |
| Priority date | — |
| Expiry date | Nov 10, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method and apparatus that compensates for variances in the resistance of the buried resistor during operation of the integrated circuit using a waveform that is representative of the thermal characteristics of the buried resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.