Switching processor threads during long latencies
US7596683B2 · kind B2 · utility
6Cited by
13References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 11, 2007 |
| Grant date | Sep 29, 2009 |
| Priority date | — |
| Expiry date | Apr 9, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes an apparatus to determine whether execution of an instruction of a first thread may require a long latency and switch to a second thread if the instruction may require the long latency. In certain embodiments, at least one additional instruction may be executed in the first thread while preparing to switch threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.