Register-based instruction optimization for facilitating efficient emulation of an instruction stream
US7596781B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2006 |
| Grant date | Sep 29, 2009 |
| Priority date | — |
| Expiry date | Oct 6, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45504
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A register-based instruction optimization is provided for facilitating efficient emulation of a target instruction stream. The optimization includes for at least one instruction in a frequently executed sequence of target instructions: confirming that at least one register is marked as a read-only register for the sequence; confirming that each register of the at least one register has been detected to have a constant value for the at least one instruction in multiple prior iterations of the executed sequence; and response thereto, optimizing the at least one instruction by replacing the at least one instruction with at least one immediate form instruction having at least one constant value encoded directly therein from the at least one register. The optimization results in an optimized sequence of target instructions, which when translated into a sequence of host instructions, is more efficiently executed by a host computing environment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.