Semiconductor memory device and a method of manufacturing the same
US7598133B2 · kind B2 · utility
5Cited by
8References
22Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 7, 2007 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Apr 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly comprise laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.