Method for forming inter-poly dielectric in shielded gate field effect transistor
US7598144B2 · kind B2 · utility
25Cited by
300References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2007 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Apr 1, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
A method of forming shielded gate trench FET includes the following steps. A trench is formed in a silicon region of a first conductivity type. A shield electrode is formed in a bottom portion of the trench. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer of conformal dielectric is formed along an upper surface of the shield electrode. A gate dielectric lining at least upper trench sidewalls is formed. A gate electrode is formed in the trench such that the gate electrode is insulated from the shield electrode by the IPD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.