Post-seed deposition process
US7598163B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Feb 15, 2007 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Feb 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12044
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method involves pattern etching a photoresist that is located on a wafer that contains a deposited seed layer to expose portions of the seed layer, plating the wafer so that plating metal builds up on only the exposed seed layer until the plating metal has reached an elevation above the seed layer that is at least equal to a thickness of the seed layer, removing the solid photoresist, and removing seed layer exposed by removal of the photoresist and plated metal until all of the exposed seed layer has been removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.