Semiconductor device including a strained superlattice and overlying stress layer and related methods
US7598515B2 · kind B2 · utility
111Cited by
58References
15Claims
0Family size
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Key dates
| Filing date | Jul 13, 2006 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Jan 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/798
Abstract
A semiconductor device may include a strained superlattice layer including a plurality of stacked groups of layers, and a stress layer above the strained superlattice layer. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.