Low noise vertical variable gate control voltage JFET device in a BiCMOS process and methods to build this device
US7598547B2 · kind B2 · utility
14Cited by
4References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2006 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Feb 4, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
Abstract
We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer contacting gate regions that connect to a gate terminal. The channel region, of which the length spans the distance between the buried layer and a source region, is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.