Semiconductor packages with enhanced joint reliability and methods of fabricating the same
US7598607B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2008 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | May 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor package with enhanced joint reliability and methods of fabricating the same. The method includes: forming package units including a semiconductor chip interposed between a bottom layer and a top layer; and sequentially stacking the package units on a substrate. The bottom layer and the top layer are formed of a material having a lower modulus than the semiconductor chip. The semiconductor package includes: at least one package unit disposed on a substrate, the package unit including a semiconductor chip having a pad, a bottom layer and a top layer substantially surrounding the semiconductor chip, and a redistribution structure overlying the top layer. The redistribution structure is electrically connected to the pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.