Transistor arrangement
US7598764B2 · kind B2 · utility
0Cited by
14References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 16, 2005 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Nov 19, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03B5/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transistor arrangement having a multiplicity of transistors interconnected with one another, having a noise detection device, which is set up for detecting the 1/f noise of at least one portion of the transistors, having a selection device, which is set up for selecting at least one of the transistors, on the basis of the ascertained 1/f noise characteristic of the transistors, in the case of which the 1/f noise is sufficiently low.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.