Flash memory device having increased over-erase correction efficiency and robustness against device variations
US7599228B1 · kind B1 · utility
12Cited by
12References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2004 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Nov 1, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is provided including circuitry for correcting an over-erased memory cell in the memory device. The memory device may include a substrate. A control gate and a floating gate may be formed over the substrate. The memory device may include a source region and a drain region. A first resistive element may be coupled between the source region and the control gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.