Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits
US7599457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2005 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Sep 21, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, a clock-and-data-recovery (CDR) system has a multi-phase clock generator that generates a plurality of phase-offset clock signals and one or more channel circuits, each receiving a (different) input data signal and all of the phase-offset clock signals and generates an output data stream and a recovered clock signal. Each channel circuit has a plurality of data registers (e.g., flip-flops), each receiving the input data signal at its clock input port and a different one of the phase-offset clock signals at its data input port, such that the flip-flop is triggered at each (rising) edge in the input data signal. The channel circuit processes the outputs from the different flip-flops to select an appropriate phase-offset clock signal for use in sampling the input data signal to generate the output data stream, where the recovered clock signal is generated from the selected phase-offset clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.